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? 2007-2014 exar corporation 1 / 18 exar.com/clc2023 rev 1d features 6mv maximum input offset voltage 0.00005% thd at 1khz 5.3nv/hz input voltage noise > 10khz -90db/-85db hd2/hd3 at 100khz, r l = 100 <-100db hd2 and hd3 at 10khz, r l = 1k rail-to-rail input and output 55mhz unity gain bandwidth 12v/s slew rate -40c to +125c operating temperature range fully specifed at 3 and 5v supplies clc2023: rohs compliant msop-8, soic-8 package options applications active flters sensor interface high-speed transducer amp medical instrumentation probe equipment test equipment smoke detectors hand-held analytic instruments current sense applications general description the clc2023 is a dual channel, high-performance, voltage feedback amplifer with low input voltage noise and ultra low distortion. the clc2023 offers 6mv maximum input offset voltage, 3.5nv/hz broadband input voltage noise, and 0.00005% thd at 1khz. it also provides 55mhz gain bandwidth product and 12v/s slew rate making them well suited for applications requiring precision dc performance and high ac performance. this high-performance amplifer also offers a rail-to-rail input and output, simplifying single supply designs and offering larger dynamic range possibilities. the input range extends beyond the rails by 300mv. the clc2023 is designed to operate from 2.5v to 12v supplies and operate over the extended temperature range of -40c to +125. typical application + - r g 0.1f 6.8f out in +2.7 + r f r in r out ? clc2023 crosstalk vs. frequency -100 -95 -90 -85 -80 -75 -70 -65 -60 0.01 0.1 1 crosstalk (db) frequency (mhz) vs = +/ - 5v, rl = 150 ? , v out = 2v pp ordering information - back page clc2023 dual, low distortion, low offset, rrio amplifier
? 2007-2014 exar corporation 2 / 18 exar.com/clc2023 rev 1d absolute maximum ratings stresses beyond the limits listed below may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. v s ................................................................................. 0v to +14v v in ............................................................ -v s - 0.5v to +v s +0.5v operating conditions supply voltage range ................................................. 2.5v to 12v operating temperature range ............................... -40c to 125c junction temperature ........................................................... 150c storage temperature range ................................... -65c to 150c lead temperature (soldering, 10s) ...................................... 260c package thermal resistance ja (msop-8) .................................................................. 200c/w ja (soic-8) ..................................................................... 150c/w package thermal resistance ( ja ), jedec standard, multi-layer test boards, still air. clc2023
? 2007-2014 exar corporation 3 / 18 exar.com/clc2023 rev 1d electrical characteristics at +3v t a = 25c, v s = +3v, r f = 1k, r l = 1k to v s /2; g = 2; unless otherwise noted. symbol parameter conditions min ty p max units frequency domain response gbwp -3db gain bandwidth product g = 10, v out = 0.05v pp 31 mhz ugbw unity gain bandwidth v out = 0.05v pp , r f = 0 50 mhz bw ss -3db bandwidth v out = 0.05v pp 24 mhz bw ls large signal bandwidth v out = 2v pp 3.3 mhz time domain t r , t f rise and fall time v out = 2v step; (10% to 90%) 150 ns t s settling time to 0.1% v out = 2v step 78 ns os overshoot v out = 2v step 0.3 % sr slew rate 2v step 11 v/s distortion/noise response hd2 2nd harmonic distortion 2v pp , 10khz, r l = 1k -98 dbc 2v pp , 100khz, r l = 100 -85 dbc hd3 3rd harmonic distortion 2v pp , 10khz, r l = 1k -95 dbc 2v pp , 100khz, r l = 100 -81 dbc thd total harmonic distortion 1v pp , 1khz, g = 1, r l = 2k 0.0005 % e n input voltage noise >10khz 5.5 nv/hz >100khz 3.9 nv/hz x talk crosstalk 1mhz 70 db dc performance v io input offset voltage 0.088 mv d vio average drift 1. 3 v/c i b input bias current -0.340 a di b average drift 0.8 na/c i os input offset current 0.2 a psrr power supply rejection ratio dc 100 db a ol open loop gain v out = v s / 2 104 db i s supply current per channel 1.85 ma input characteristics r in input resistance non-inverting, g = 1 30 m c in input capacitance 1. 1 pf cmir common mode input range -0.3 to 3.3 v cmrr common mode rejection ratio dc, v cm = 0.5v to 2.5v 75 db output characteristics v out output swing r l = 150 0.085 to 2.80 v r l = 1k 0.04 to 2.91 v i out output current +57, -47 ma i sc short circuit current v out = v s / 2 +65, -52 ma clc2023
? 2007-2014 exar corporation 4 / 18 exar.com/clc2023 rev 1d electrical characteristics at 5v t a = 25c, v s = 5v, r f = 1k, r l = 1k to gnd; g = 2; unless otherwise noted. symbol parameter conditions min ty p max units frequency domain response gbwp -3db gain bandwidth product g = 10, v out = 0.05v pp 35 mhz ugbw unity gain bandwidth v out = 0.05v pp , r f = 0 55 mhz bw ss -3db bandwidth v out = 0.05v pp 25 mhz bw ls large signal bandwidth v out = 2v pp 3.6 mhz time domain t r , t f rise and fall time v out = 2v step; (10% to 90%) 125 ns t s settling time to 0.1% v out = 2v step 80 ns os overshoot v out = 2v step 0.3 % sr slew rate 4v step 12 v/s distortion/noise response hd2 2nd harmonic distortion 2v pp , 10khz, r l = 1k -125 dbc 2v pp , 100khz, r l = 100 -90 dbc hd3 3rd harmonic distortion 2v pp , 10khz, r l = 1k -127 dbc 2v pp , 100khz, r l = 100 -85 dbc thd total harmonic distortion 1v pp , 1khz, g = 1, r l = 2k 0.00005 % e n input voltage noise >10khz 5.3 nv/hz >100khz 3.5 nv/hz x talk crosstalk 1mhz 70 db dc performance v io input offset voltage -6 0.050 6 mv d vio average drift 1. 3 v/c i b input bias current -2.6 -0.30 2.6 a di b average drift 0.85 na/c i os input offset current 0.2 0.7 a psrr power supply rejection ratio dc 82 100 db a ol open loop gain v out = v s / 2 95 115 db i s supply current per channel 2.2 2.75 ma input characteristics r in input resistance non-inverting, g = 1 30 m c in input capacitance 1 pf cmir common mode input range 5.3 v cmrr common mode rejection ratio dc, v cm = -3v to 3v 70 85 db output characteristics v out output swing r l = 150 -4.826 to 4.534 v r l = 1k -4.7 -4.93 to 4.85 4.7 v i out output current +60, -48 ma i sc short circuit current v out = v s / 2 +65, -52 ma clc2023
? 2007-2014 exar corporation 5 / 18 exar.com/clc2023 rev 1d clc2023 pin assignments msop-8 / soic-8 pin no. pin name description 1 out1 output, channel 1 2 -in1 negative input, channel 1 3 +in1 positive input, channel 1 4 -v s negative supply 5 +in2 positive input, channel 2 6 -in2 negative input, channel 2 7 out2 output, channel 2 8 +v s positive supply clc2023 pin confguration msop-8 / soic-8 - + - + 1 2 3 4 out1 -in1 +in1 -v s +v s out2 -in2 +in2 8 7 6 5 clc2023
? 2007-2014 exar corporation 6 / 18 exar.com/clc2023 rev 1d typical performance characteristics t a = 25c, v s = 5v, r f = 1k, r l = 1k, g = 2; unless otherwise noted. frequency response vs. v out frequency response vs. r l frequency response vs. c l frequency response vs. c l without r s non-inverting frequency response inverting frequency response - 9 - 6 - 3 0 3 0.1 1 10 100 normalized gain (db) frequency (mhz) g = 1 r f = 0 g = 2 g = 5 g = 10 v out = 0.05v pp - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 1 0.1 1 10 100 normalized gain (db) frequency (mhz) g = - 1 g = - 2 g = - 5 g = - 10 v out = 0.05v pp - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 1 0.1 1 10 100 normalized gain (db) frequency (mhz) c l = 1000pf r s = 7.5 c l = 500pf r s = 10 c l = 3000pf r s = 4 v out = 0.05v pp - 8 - 6 - 4 - 2 0 2 4 0.1 1 10 100 normalized gain (db) frequency (mhz) c l = 500pf c l = 300pf c l = 100pf c l = 50pf c l = 10pf v out = 0.05v pp rs = 0 - 9 - 6 - 3 0 3 0.1 1 10 100 normalized gain (db) frequency (mhz) v out = 1v pp v out = 2v pp v out = 4v pp - 6 - 5 - 4 - 3 - 2 - 1 0 1 2 0.1 1 10 100 normalized gain (db) frequency (mhz) r l = 2.5k v out = 0.05v pp r l = 1k r l = 150 r l = 50 clc2023
? 2007-2014 exar corporation 7 / 18 exar.com/clc2023 rev 1d typical performance characteristics t a = 25c, v s = 5v, r f = 1k, r l = 1k, g = 2; unless otherwise noted. -3db bandwidth vs. output voltage at v s = 3v -3db bandwidth vs. output voltage frequency response vs. v out at v s = 3v frequency response vs. r l at v s = 3v non-inverting frequency response at v s = 3v inverting frequency response at v s = 3v - 9 - 6 - 3 0 3 0.1 1 10 100 normalized gain (db) frequency (mhz) g = 1 r f = 0 g = 2 g = 5 g = 10 v out = 0.05v pp - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 1 0.1 1 10 100 normalized gain (db) frequency (mhz) g = - 1 g = - 2 g = - 5 g = - 10 v out = 0.05v pp - 9 - 6 - 3 0 3 0.1 1 10 100 normalized gain (db) frequency (mhz) v out = 1v pp v out = 2v pp v out = 2.5v pp - 6 - 5 - 4 - 3 - 2 - 1 0 1 2 0.1 1 10 100 normalized gain (db) frequency (mhz) r l = 2.5k v out = 0.05v pp r l = 1k r l = 150 r l = 50 0 3 6 9 12 15 18 21 24 0.0 0.5 1.0 1.5 2.0 2.5 - 3db bandwidth (mhz) v out (v pp ) 0 3 6 9 12 15 18 21 24 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 - 3db bandwidth (mhz) v out (v pp ) clc2023
? 2007-2014 exar corporation 8 / 18 exar.com/clc2023 rev 1d typical performance characteristics t a = 25c, v s = 5v, r f = 1k, r l = 1k, g = 2; unless otherwise noted. cmrr vs. frequency psrr vs. frequency input voltage noise cmir at v s = 3v open loop gain and phase vs. cmir - 525 - 450 - 375 - 300 - 225 - 150 - 75 0 - 60 - 40 - 20 0 20 40 60 80 10 100 1,000 10,000 100,000 1,000,000 phase ( ) gain (db) freq (khz) gain phase -0.1 0 0.1 0.2 0.3 0.4 0.5 -6 -4 -2 0 2 4 6 vout (v) vcm(v) 2 3 4 5 6 7 8 9 10 11 12 13 14 0.0001 0.001 0.01 0.1 1 input voltage noise (nv/hz) clc2023
? 2007-2014 exar corporation 9 / 18 exar.com/clc2023 rev 1d typical performance characteristics t a = 25c, v s = 5v, r f = 1k, r l = 1k, g = 2; unless otherwise noted. thd vs. frequency 2nd harmonic distortion vs. v out 3rd harmonic distortion vs. v out 2nd harmonic distortion vs. r l 3rd harmonic distortion vs. r l - 110 - 100 - 90 - 80 - 70 - 60 - 50 100 200 300 400 500 600 700 800 900 1000 distortion (dbc) frequency (khz) r l = 100 v out = 2v pp r l = 10k r l = 1k r l = 500 - 110 - 100 - 90 - 80 - 70 - 60 - 50 100 200 300 400 500 600 700 800 900 1000 distortion (dbc) frequency (khz) r l = 100 v out = 2v pp r l = 10k r l = 1k r l = 500 - 100 - 90 - 80 - 70 - 60 - 50 - 40 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 distortion (dbc) output amplitude (v pp ) rf=rl=10k rf=rl=1k freq = 500khz - 100 - 90 - 80 - 70 - 60 - 50 - 40 - 30 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 distortion (dbc) output amplitude (v pp ) rf=rl=10k rf=rl=1k freq = 500khz - 100 - 95 - 90 - 85 - 80 - 75 - 70 - 65 100 200 300 400 500 600 700 800 900 1000 thd (db) frequency (khz) v out = 1v pp r l = 1k a v +1 clc2023
? 2007-2014 exar corporation 10 / 18 exar.com/clc2023 rev 1d typical performance characteristics t a = 25c, v s = 5v, r f = 1k, r l = 1k, g = 2; unless otherwise noted. thd vs. frequency at v s = 3v 2nd harmonic distortion vs. v out at v s = 3v 3rd harmonic distortion vs. v out at v s = 3v 2nd harmonic distortion vs. r l at v s = 3v 3rd harmonic distortion vs. r l at v s = 3v - 100 - 90 - 80 - 70 - 60 - 50 - 40 100 200 300 400 500 600 700 800 900 1000 distortion (dbc) frequency (khz) r l = 100 v out = 2v pp r l = 10k r l = 1k r l = 500 - 100 - 90 - 80 - 70 - 60 - 50 - 40 100 200 300 400 500 600 700 800 900 1000 distortion (dbc) frequency (khz) r l = 100 v out = 2v pp r l = 10k r l = 1k r l = 500 - 100 - 90 - 80 - 70 - 60 - 50 - 40 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 distortion (dbc) output amplitude (v pp ) rf=rl=10k rf=rl=1k freq = 500khz - 100 - 90 - 80 - 70 - 60 - 50 - 40 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 distortion (dbc) output amplitude (v pp ) rf=rl=10k rf=rl=1k freq = 500khz - 100 - 95 - 90 - 85 - 80 - 75 - 70 - 65 100 200 300 400 500 600 700 800 900 1000 thd (db) frequency (khz) v out = 1v pp r l = 1k a v +1 clc2023
? 2007-2014 exar corporation 11 / 18 exar.com/clc2023 rev 1d typical performance characteristics t a = 25c, v s = 5v, r f = 1k, r l = 1k, g = 2; unless otherwise noted. large signal pulse response large signal pulse response at v s = 3v small signal pulse response small signal pulse response at v s = 3v - 0.75 - 0.5 - 0.25 0 0.25 0.5 0.75 0 0.5 1 1.5 2 voltage (v) time (ns) 1.35 1.4 1.45 1.5 1.55 1.6 1.65 0 0.5 1 1.5 2 voltage (v) time (ns) - 6 - 4 - 2 0 2 4 6 0 1 2 3 4 5 6 7 8 9 10 voltage (v) time (ns) 0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 voltage (v) time (ns) clc2023
? 2007-2014 exar corporation 12 / 18 exar.com/clc2023 rev 1d application information basic information figures 1 and 2 illustrate typical circuit confgurations for non-inverting, inverting, and unity gain topologies for dual supply applications. they show the recommended bypass capacitor values and overall closed loop gain equations. + - r f 0.1f 6.8f output g = 1 + (r f /r g ) input +v s -v s r g 0.1f 6.8f r l figure 1: typical non-inverting gain circuit + - r f 0.1f 6.8f output g = - (r f /r g ) for optimum input offset voltage set r 1 = r f || r g input +v s -v s 0.1f 6.8f r l r g r 1 figure 2: typical inverting gain circuit power dissipation power dissipation should not be a factor when operating under the stated 500 load condition. however, applications with low impedance, dc coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond its intended operating range. maximum power levels are set by the absolute maximum junction rating of 150c. to calculate the junction temperature, the package thermal resistance value theta ja ( ja ) is used along with the total die power dissipation. t junction = t ambient + ( ja p d ) where t ambient is the temperature of the working environment. in order to determine p d , the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. p d = p supply - p load supply power is calculated by the standard power equation. p supply = v supply i rmssupply v supply = v s+ - v s- power delivered to a purely resistive load is: p load = ((v load ) rms 2 )/rload eff the effective load resistor (rload eff ) will need to include the effect of the feedback network. for instance, rload eff in figure 2 would be calculated as: r l || (r f + r g ) these measurements are basic and are relatively easy to perform with standard lab equipment. for design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. here, p d can be found from p d = p quiescent + p dynamic - p load quiescent power can be derived from the specifed i s values along with known supply voltage, v supply . load power can be calculated as above with the desired signal amplitudes using: (v load ) rms = v peak / 2 ( i load ) rms = ( v load ) rms / rload eff the dynamic power is focused primarily within the output stage driving the load. this value can be calculated as: p dynamic = (v s+ - v load ) rms ( i load ) rms assuming the load is referenced in the middle of the power rails or v supply /2. figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the packages available. clc2023
? 2007-2014 exar corporation 13 / 18 exar.com/clc2023 rev 1d 0 0.5 1 1.5 -40 -20 0 20 40 60 80 100 120 maximum power dissipation (w) ambient temperature ( c) msop -8 soic -8 figure 3. maximum power derating driving capacitive loads increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. use a series resistance, r s , between the amplifer and the load to help improve stability and settling performance. refer to figure 4. + - r f input output r g r s c l r l figure 4. addition of r s for driving capacitive loads the clc2023 is capable of driving up to 300pf directly, with no series resistance. directly driving 500pf causes over 4db of frequency peaking, as shown in the plot on page 6. table 1 provides the recommended r s for various capacitive loads. the recommended r s values result in 1db peaking in the frequency response. the frequency response vs. c l plots, on page 6, illustrate the response of the clc2023. c l (pf) r s () -3db bw (mhz) 500 10 27 1000 7. 5 20 3000 4 15 table 1: recommended r s vs. c l for a given load capacitance, adjust r s to optimize the tradeoff between settling time and bandwidth. in general, reducing r s will increase bandwidth at the expense of additional overshoot and ringing. overdrive recovery an overdrive condition is defned as the point when either one of the inputs or the output exceed their specifed voltage range. overdrive recovery is the time needed for the amplifer to return to its normal or linear operating point. the recovery time varies based on whether the input or output is overdriven and by how much the ranges are exceeded. the clc2023 will typically recover in less than 20ns from an overdrive condition. figure 5 shows the clc2023 in an overdriven condition. - 2 - 2 - 1 - 1 0 1 1 2 2 - 3 - 2 - 1 0 1 2 3 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 output voltage (v) input voltage (v) time (us) output input v in = .8v pp g = 5 figure 5 oerdrie recoery considerations for offset and noise performance offset analysis there are three sources of offset contribution to consider; input bias current, input bias current mismatch, and input offset voltage. the input bias currents are assumed to be equal with and additional offset current in one of the inputs to account for mismatch. the bias currents will not affect the offset as long as the parallel combination of r f and r g matches r t . refer to figure 6. in r g r f r t r l +v s -v s ? + clc2023 figure 6: circuit for evaluating offset the frst place to start is to determine the source resistance. if it is very small an additional resistance may need to be added to keep the values of r f and r g to practical levels. for this analysis we assume that r t is the total resistance present on the non-inverting input. this gives us one equation that we must solve: clc2023
? 2007-2014 exar corporation 14 / 18 exar.com/clc2023 rev 1d r t = r g ||r f this equation can be rearranged to solve for r g : r g = (r t * r f ) / (r f - r t ) the other consideration is desired gain (g) which is: g = (1 + r f /r g ) by plugging in the value for r g we get r f = g * r t and r g can be written in terms of r t and g as follows: r g = (g * r t ) / (g - 1) the complete input offset equation is now only dependent on the voltage offset and input offset terms given by: v i o s = v i o ( ) 2 + i o s ? r t ( ) 2 and the output offset is: v o o s = g ? v i o ( ) 2 + i o s ? r t ( ) 2 noise analysis the complete equivalent noise circuit is shown in figure 7. r g r f r l ? + clc2023 + ? + ? r g + ? + ? + ? w figure 7: complete equivalent noise circuit the complete noise equation is given by: v 2 o = v 2 orext + e n 1 + r f r g 2 + i b p ? r t 1 + r f r g 2 + i b n ? r f ( ) 2 where v orext is the noise due to the external resistors and is given by: = e n 1 + r f r g 2 + e g ? r f r g 2 + e 2 f v 2 o the complete equation can be simplifed to: = 3 ? 4 k t ? g ? r t ( ) + e n g ( ) 2 + 2 ? i n ? r t ( ) 2 v 2 o its easy to see that the effect of amplifer voltage noise is proportionate to gain and will tend to dominate at large gains. the other terms will have their greatest impact at large r t values at lower gains. layout considerations general layout and supply bypassing play major roles in high frequency performance. exar has evaluation boards to use as a guide for high frequency layout and as an aid in device testing and characterization. follow the steps below as a basis for high frequency layout: include 6.8f and 0.1f ceramic capacitors for power supply decoupling place the 6.8f capacitor within 0.75 inches of the power pin place the 0.1f capacitor within 0.1 inches of the power pin remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance minimize all trace lengths to reduce series inductances refer to the evaluation board layouts below for more information. evaluation board information the following evaluation boards are available to aid in the testing and layout of these devices: evaluation board # products ceb006 clc2023 in soic-8 ceb010 clc2023 in msop-8 evaluation board schematics evaluation board schematics and layouts are shown in figures 8-12 these evaluation boards are built for dual- supply operation. follow these steps to use the board in a single-supply application: 1. short -v s to ground. 2. use c3 and c4, if the -v s pin of the amplifer is not directly connected to the ground plane. clc2023
? 2007-2014 exar corporation 15 / 18 exar.com/clc2023 rev 1d figure 8. ceb006 & ceb010 schematic figure 9. ceb006 top view figure 10. ceb006 bottom view figure 11. ceb010 top view figure 12. ceb010 bottom view clc2023
? 2007-2014 exar corporation 16 / 18 exar.com/clc2023 rev 1d mechanical dimensions soic-8 package clc2023
? 2007-2014 exar corporation 17 / 18 exar.com/clc2023 rev 1d msop-8 package clc2023
for further assistance: email: c ustomersupport@exar.com or hpatechsupport@exar.com exar technical documentation: http://www.exar.com/techdoc/ exar corporation headquarters and sales offices 48760 kato road tel.: +1 (510) 668-7000 fremont, ca 94538 - usa fax: +1 (510) 668-7001 ? 2007-2014 exar corporation 18 / 18 exar.com/clc2023 rev 1d ordering information part number package green operating temperature range packaging clc2023 ordering information clc2023imp8x msop-8 ye s -40c to +125c tape & reel clc2023imp8mtr msop-8 ye s -40c to +125c mini tape & reel CLC2023IMP8EVB evaluation board n/a n/a n/a clc2023iso8x soic-8 ye s -40c to +125c tape & reel clc2023iso8mtr soic-8 ye s -40c to +125c mini tape & reel clc2023iso8evb evaluation board n/a n/a n/a moisture sensitivity level for all parts is msl-1. revision history revision date description 1d (ecn 1451-06) december 2014 reformat into exar data sheet template. updated ordering information table to include mtr and evb part numbers. increased i temperature range from +85 to +125c. removed a temp grade parts, since i is now equivalent. updated thermal resistance numbers and package outline drawings. notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specifc application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. clc2023

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